1. Field of the Invention
The present invention relates to a data transfer control apparatus for controlling data transfer on a data bus such as a PCI (Peripheral Component Interconnect) bus connected to a microprocessor through a bridge circuit.
2. Description of the Related Art
As a general-purpose bus for connecting external devices to a personal computer or the like, a PCI bus has been increasingly employed. The PCI bus is connected to a microprocessor through a bridge circuit. The PCI bus is designed to enable connection of external peripheral devices such as a memory module conforming to the PCI bus standard.
Such data transfer through a PCI bus includes DMA (Direct Memory Access) transfer and MPC (Microprocessor Controller) transfer.
DMA transfer refers to direct data transfer between peripheral devices connected to a PCI bus not through a microprocessor. MPC transfer refers to data transfer through a PCI bus performed by an MPC which controls data, processing or the like in accordance with directions from a microprocessor (not shown).
The DMA transfer is controlled by a SCSI (Small Computer System Interface) protocol controller for controlling a SCSI which is an interface between peripheral devices not through a microprocessor. A configuration of such a data transfer control apparatus in the prior art is shown in FIG. 1.
The data transfer control apparatus in the prior art comprises a MPC 2, a bridge circuit 17, a PCI bus 6, a SPC (SCSI protocol controller) 4, a memory module 5, and a local memory 3.
Local memory 3 is a memory connected to a microprocessor (not shown) not through PCI bus 6. MPC 2 effects data control, data processing or the like in accordance with directions from the microprocessor. SPC 4 controls a SCSI. Memory module 5 is connected to PCI bus 6 as an external memory. Bridge circuit 17 performs connection between MPC 2 and local memory 3 as well as MPC 2 and PCI bus 6.
When DMA transfer is performed in the prior art data transfer control apparatus, as shown in FIG. 2, SPC 4 transfers data directly to and from memory module 5 through PCI bus 6. When MPC transfer is performed in the prior art data transfer control apparatus, as shown in FIG. 3, MPC 2 transfers data to and from memory module 5 through bridge circuit 17 and PCI bus 6.
The DMA transfer and MPC transfer, both through PCI bus 6, are unable to be performed simultaneously. For this reason, if a transfer request for one of data transfer is made while the other data transfer is being performed, the one data transfer is controlled to be performed after the completion of the other data transfer.
However, since a microprocessor executes not only control for data transfer but also other various control, a long time required only for data transfer control exerts an influence upon other control, leading to an influence upon the entire device such as a personal computer. Therefore, control is generally made to perform MPC transfer with a higher priority than DMA transfer.
Next, operation will be described with reference to a flow chart in FIG. 4 in a case where a request for MPC transfer is made from MPC 2 while DMA transfer is being performed in the prior art data transfer control apparatus.
First, DMA transfer is performed at step 101. Bridge circuit 17 receives an MPC transfer instruction from MPC 2 before the DMA transfer is completed at step 102, and the preceding DMA transfer is suspended at step 103. MPC transfer is performed at step 104 and the DMA transfer is resumed after the completion of the MPC transfer at step 105.
In this manner, in the prior art data transfer control apparatus, if an instruction for MPC transfer is received during execution of DMA transfer on the PCI bus, the preceding DMA transfer is suspended to perform MPC transfer regardless of an influence of the MPC transfer upon the PCI bus, and the DMA transfer is resumed after the completion of the MPC transfer. As a result, when the PCI bus is occupied with MPC transfer for a long time because an MPC transfer instruction is frequently generated or the amount of data transfer for MPC transfer is large, DMA transfer is unable to proceed, causing a data transfer rate to be lowered.
It is an object of the present invention to provide a data transfer control apparatus capable of preventing a data transfer rate from being lowered due to DMA transfer not proceeding even when a PCI bus is occupied with MPC transfer for a long time because of a frequently generated MPC transfer instruction or a large amount of data transfer for MPC transfer.
To achieve the aforementioned object, a data transfer control apparatus according to the present invention has a bridge circuit that includes a monitoring means. When an MPC transfer instruction is issued during DMA transfer, the monitoring means measures a time period over which a data bus is to be occupied with MPC transfer. When the data bus is to be occupied with the MPC transfer for a predetermined time period, the monitoring means does not suspend the DMA transfer but performs MPC transfer after the completion of the DMA transfer. Therefore, DMA transfer is not suspended by MPC transfer for a long time to prevent a data transfer rate from being lowered, thereby improving throughput of data transfer.